Processor Organization and RISC

The processor executes instructions via two operations:

1. Move data from one place to another
2. Perform data processing through ALU

The data are stored in registers inside CPU, and operations controlled by control signals generated by control units.

Data movement is controled by control signals, generated by the control unit:

A movement operation $A \leftarrow B$ requires 2 control signals:

1. Tell PC to put contnet onto CPU bus
2. Tell MAR to get value from CPU bus

Other operations may require more control signals, such as:

• ALU operations
• Read/write external memory

Recall the different FDE stages of an instruction.

We can increase the throughput of the CPU by processing different stages of different instructions simultaneously, by having different hardware used for each stage, in one clock cycle.

Ideally, this increases the throughput be 1 instruction per clock cycle ($CPI$).

Note: [modern processors] don't have memory operands, so no CO stage.

Notes:

• $\text{Clock cycle time} = \frac{1}{\text{Clock rate}}$

Ways to improving (reducing) execution time:

• Simplify instruction set and use hardwired logic $\to \text{Clock rate} \Uparrow, \text{Instruction Count} \uparrow$
• Extensive pipelining $\to \text{CPI} \Downarrow$

There is overall improvement in performance, as increase in instruction count (and code size) is usually very small.

Consider the two set of instructions:

Without registers:

ADD A, B, C
ADD D, C, F
ADD B, F, C
---
Memory access count: 9

With registers:

LD A, R1
LD B, R2
ADD R1, R2, R3
LD D, R4
ADD R4, R3, R5
ADD R2, R5, R3
ST R3, C
ST R5, D
---
Memory access count: 5 < 9